1. Field of the Invention
The present invention relates to a manufacturing method of a semiconductor device and more particularly to a manufacturing method of an aluminium (Al) interconnection utilized for a multi-layered interconnection in a semiconductor integrated-circuit device.
2. Description of the Related Art
For an interconnection layer in a semiconductor device, aluminium (Al), Alxe2x80x94Cu alloy in which copper is added into Al or the like has been in use for some time. Generally, in a method of forming an interconnection, a resist-pattern is first formed by means of photolithography (PR) and, then, using that pattern as a mask, dry etching is applied thereto. For an Al interconnection, however, because of a particularly high reflectance of the Al surface, an anti-reflection layer of TiN or the like is formed and a resist pattern is formed thereon. Further, when an interconnection is formed to have a multi-layered structure, a Ti layer is formed between the anti-reflection layer and the Al layer, since the contact resistance between an upper layer interconnection and a lower layer interconnection becomes too high if the TiN layer alone is used.
FIGS. 3(a)-(g) are schematic cross-sectional views illustrating the steps of a method of forming an interconnection. First, on a semiconductor substrate having an insulating surface such as a plasma SiO2 film 1, a barrier layer 4 consisting of, for example, a Ti layer 2a and a TiN layer 3a is formed and, over that, an Al layer 5 made of either a simple substrate of Al or an Alxe2x80x94Cu alloy is formed, and thereon an anti-reflection layer 6 consisting of a Ti layer 2b and a TiN layer 3b is further formed to make up a multi-layered structure (FIG. 3(a)).
Next, after a resist pattern 7 is formed into the shape of an interconnection pattern (FIG. 3(b)), using that pattern as a mask, said multi-layered structure is patterned by means of dry etching (FIG. 3(c)).
After removing the resist (FIG. 3(d)), an interlayer insulating film 9 is grown (FIG. 3(e)), and then the surface of the interlayer insulating film 9 is planarized by the CMP (Chemical Mechanical Polishing) method (FIG. 3(f)). Finally, in order to degas the interlayer insulating film, a heat treatment is applied thereto in a nitrogen atmosphere under the condition that the temperature is 300 to 500xc2x0 C., and thereby the formation of one layer within a multi-layered interconnection is accomplished (FIG. 3(g)).
However, heating at the time of the formation of the interlayer insulating film or in the final step of the heat treatment induces the alloying reaction to make an AlTi alloy in the vicinity of the interface between the Al layer 5 and its overlying Ti layer 2 and forms an alloy layer 8. This leads to the creation of voids 11 in the Al metal interconnection layer 5, which gives rise to problems such as the severance of the interconnection.
Meanwhile, it is known that the resistance against electromigration can be raised by sandwiching an Al interconnection layer with the Ti layers, though the composition of the layers is somewhat different from that of the present invention, and there also has been proposed a method wherein, after forming a Ti/Al/Ti layered structure, respective Ti layers and the Al layer therein are positively made to react with each other by heating the substrate up to a temperature of 300 to 500xc2x0 C. so as to form a Al3Ti/Al/Al3Ti layered structure.
Further, in JP-A-10-125676, it is disclosed that, if a heat treatment is applied to an Al alloy layer that is arranged to lie next to an alloy layer of Al and either a refractory metal or a transition metal, in this instance, an Alxe2x80x94Ti layer, the amount of a reduction in the film thickness of the Al alloy layer can be made smaller, compared with that in the case a heat treatment is applied to an Al alloy layer lying next to a Ti layer, and, therefore, an increase in the resistance of the Al interconnection can be controlled.
In order to prevent voids to be created in the Al layer 5, a method in which a heat treatment is performed preliminarily to induce the alloying reaction in a similar way to the above methods, and, thereafter, patterning, formation of an interlayer insulating film, planarization and annealing for degassing are performed can be considered. The investigations conducted by the present inventors, however, found this method has various problems.
The first problem is that, when patterning is performed after an alloy is made, etching residues are generated so that a problem of the current leakage may occur. This results from a fact that the alloy layer, in comparison with normal metal layers, is hard to etch and besides granular crystals are formed therein as an alloy is made and those grains are liable to remain as etching residues.
The second problem is that, unless the proceeding of the alloying reaction within the remaining patterned portions of the multi-layered structure is thorough, the heat treatment for degassing starts the alloying reaction again and creates voids. Consequently, the duration of the first heat treatment must be set long enough to allow the alloying reaction to proceed to the full.
Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device having an Al interconnection wherein creation of voids is prevented and the required duration of a heat treatment is not inappropriately long for practical purposes.
In light of the above problems, the present invention provides a method of manufacturing a semiconductor device; which comprises the steps of:
forming, on a semiconductor substrate having an insulating surface, a multi-layered structure comprising a barrier layer, an interconnection metal layer made of Al or an alloy whose main component is Al, a Ti layer to lie over said interconnection metal layer and an anti-reflection layer to lie over said Ti layer;
patterning said multi-layered structure into the shape of an interconnection pattern;
carrying out a heat treatment in which said patterned structure is heated so as to bring about an alloying reaction between Al in said interconnection metal layer and Ti, at least in the vicinity of the interface between said interconnection metal layer and Ti layer, and form an AlTi alloy layer;
growing an interlayer insulating film, burying said patterned interconnection;
planarizing the interlayer insulating film; and
carrying out another heat treatment in order to degas the interlayer insulating film.
Further, the present invention provides a method of manufacturing a semiconductor device; which comprises the steps of:
forming, on a semiconductor substrate having an insulating surface, a multi-layered structure comprising a barrier layer, an interconnection metal layer made of Al or an alloy whose main component is Al, a Ti layer to lie over said interconnection metal layer, an anti-reflection layer to lie over said Ti layer and a SiO2 layer to lie over said anti-reflection layer;
patterning the SiO2 layer, the anti-reflection layer and the Ti layer in said multi-layered structure into the shape of an interconnection pattern;
carrying out a heat treatment in which said patterned structure is heated so as to bring about an alloying reaction between Al in said interconnection metal layer and Ti, at least in the vicinity of the interface between said interconnection metal layer and Ti layer, and form an AlTi alloy layer;
patterning the interconnection metal layer and the barrier layer, using said patterned SiO2 layer as a mask;
growing an interlayer insulating film, burying said patterned interconnection;
planarizing the interlayer insulating film; and
carrying out another heat treatment in order to degas the interlayer insulating film.
In the present invention, before forming an AlTi alloy that is hard to etch, either an interconnection pattern is formed or layers lying over the Ti layer in which the AlTi alloy is to be formed are patterned. These techniques suppress the generation of etching residues and thus eliminate the problem of the current leakage, and, in addition, prevent voids from being created within the Al interconnection layer in the step of the heat treatment of the post-treatment steps so that a method of manufacturing a semiconductor device with a high yield can be provided.